(1) Field of the Invention
The present invention relates to flat panel Field Emission Displays (FEDs), and more particularly, to a method for manufacturing an array of micro-miniature field emission cathode structures having high aspect ratios and improved electrical characteristics.
(2) Description of the Prior Art
There is a strong need in the electronics industry to replace the traditional cathode ray tube (CRT) with thin, lightweight display panels. For example, one application for low power, low cost flat panel displays (FPD) is in the computer industry for portable computers, such as laptop computers. The most commonly used display panel, at the current time, is the liquid crystal display (LCD) because of its' relatively low cost and power consumption. However, because of the slow optical response time of the liquid crystal to turn on or off a pixel (the discrete dots on the screen making up the image) and because of the relatively poor luminosity, for example, as measured in foot-Lamberts, other display technologies are actively being explored.
One alternative display technology having the potential to satisfy the required faster response times and increased brightness are flat panel Field Emission Displays (FEDs). The flat panel FED can be considered as an array of micro-miniature cold cathode electron emitters mounted on a substrate or backing plate from which emitted electrons are accelerated across the thickness of the evacuated panel to excite an electroluminescent material (phosphors) comprising the pixels (dots) on a transparent plate that serves as both the anode and the viewing screen. The array of very small conical shaped electron emitters are electrically accessed, for peripheral control and image forming circuits, by an array of conducting lines that form columns and rows. The columns lines form the cathode contact on which the conical electron emitters are formed. The rows of conducting lines are separated by an insulating layer from the column lines, formed on the backing plate, and both the row conducting lines and the insulator have opening over the column lines on which the electron emitter is then formed. The row lines having the edge of the openings in close proximity to the emitter tip function as the electrically addressable gate electrode or control grid for the individual electron emitters.
The design of these emitter structures are very critical to the performance of the flat panel FED and are best understood by reference to the prior art depicted schematically in cross sectional view, in FIG. 1. A more detailed description is provide by C. A. Sprindt in U.S. Pat. No. 5,064,396, but briefly, the method is a follows. An array of parallel lower electrodes 14 are formed on a insulating baseplate 18. An insulating layer 16 is deposited over the electrodes 14 and then a second array of upper electrodes 12 are formed perpendicular to the first array of electrodes 14 over the insulating layer 16. Circular openings 20 are formed in the upper electrodes 12 and the insulating layer 16 over and to the lower electrodes 14. Not shown in FIG. 1, a conducting material is deposited next by physical evaporative deposition normal to the surface, while the overall structure is rotated about an axis normal to the electrodes 12 and 14. Prior to the physical evaporative deposition step, a release layer, such as aluminum oxide is deposited (not shown) for lifting off the conductive layer over the upper electrode 12. During the physical evaporative deposition of the conductive layer, as shown in FIG. 1, conical electron emitter structures 26, are formed in the openings, such as opening 20 in FIG. 1, on the lower electrode 14. The conical shape results from the continuous reduction in the opening 21 of electrode 12 by the accumulation of the conductive layer on the upper electrode during the deposition process. The final electron emitting cathode structure formed by the lower and upper electrodes 14 and 12 and the emitter 26 is shown in FIG. 1 after the conductive layer is lifted off by etching the release layer.
The design of the electron emitting cathode for optimum efficiency is dependent on several process design parameters. For example, as is well known in electro-statics, the tip 28 of the conical emitter 26 should have the smallest radius of curvature, be essentially coplanar and symmetrically center in the upper electrode opening 20 and be as close to the edge of electrode 12 as is physically possible without shorting. This is to provide the highest electron emission efficiency, which is a function of the electric field E at the tip and proportional to the voltage difference between the emitter tip 28 and the upper electrode 12 and inversely proportional to the spacing R, as shown in FIG. 1. Another important design consideration is to make the distributive capacitance between the lower cathode electrode 14 and the grid or upper gate electrode 12 as small as possible The reduced capacitance minimize the RC time constant and thereby maximizes the AC circuit performance during the continuous pulse mode operation of the circuit.
Unfortunately, the nature of the deposition process for forming the conical electron emitter 26 requires that the diameter D of the opening in electrode 12 be about equal to the height H between the electrodes 12 and 14 (aspect ratio (H/D)=1.0) if the emitter tip 28 is to be coplanar with electrode 12. This results in a relatively large and undesirable distance R, as shown in FIG. 1. If the diameter of the opening 20 is decreased, then the spacing H must also be reduced to retain an aspect ratio of 1.0 and coplanarity, and this results in increased capacitance.
One invention which discloses a method for reducing the capacitance is by S. H. Holmberg, in U.S. Pat. No. 5,075,591 which forms a conical electron emitter that is coplanar with the gate electrode. A cross sectional view is schematically shown in FIG. 2 of this cathode structure. The method involves using two dissimilar dielectric layers 32 and 34 between the lower electrode 28 and the upper electrodes 30 and then using additional masking and etching steps to from a larger opening 38 and a smaller opening 36 in the dielectric layers 34 and 32, respectively. The conical emitter 29, coplanar with the upper gate electrode 30, is formed in the smaller opening 36 on the lower cathode electrode 28 which is itself supported by an insulating substrate 26. The capacitance is thereby reduced in areas having the thicker overlapping layers 32 and 34, however, the method requires additional masking and etching processing steps.
Another approach for reducing the capacitance and/or reducing the distance or gap R between the emitter tip and the upper gate electrode is also described in U.S. Pat. No. 5,064,396 by C. A. Spindt. The method is depicted in FIG. 3, and involves increasing the dielectric layer 16 to reduce the capacitance, or alternatively decreasing the diameter D of the opening 20 so that the aspect ratio is greater than 1.0 For example, the aspect ratio can have a value of about 2.0. Then the electron emitter 26 is formed as before by physical evaporative deposition. However, since the aspect ratio (H/D) of the opening is greater than 1.0, the height of the electron emitter 26 is less than the thickness of the dielectric layer 16 and therefore noncoplanar with the upper electrode 12. The improved Spindt invention utilizes two or more evaporative depositions and lift-offs to form an extension 44 on the electron emitter 26, so as to make the tip coplanar with electrode 12.
Although the above described methods of the prior art reduce the distributed capacitance while maintaining a narrow gap between the emitter tip and gate electrode, and thereby improve the circuit performance, the processing is more complex and therefore the manufacturing process is less cost effective and more susceptible to process yield loss.